1. Field of the Invention
The present invention relates to a method of forming contact holes in a semiconductor device, and more particularly to a method of forming contact holes in a cell array region and a peripheral region of a semiconductor device.
2. Description of the Related Art
In ULSI (Ultra Large Scale Integration) device fabrication, as design rules for semiconductor devices become smaller and smaller, sufficient alignment margin can hardly be secured, for example, when aligning a contact plug with a semiconductor layer or interconnect layer underlying the contact plug. Accordingly, for micron level semiconductor devices, a manufacturing process that permits the contact plug to be formed by self alignment with a semiconductor layer or interconnect layer underlying the contact plug is employed.
Thus, Self-aligned contact (SAC) techniques have been used to secure sufficient alignment margin by selectively etching one layer against another layer, e.g., selectively etching an oxide layer against a nitride layer. Such SAC techniques are mostly employed to form bit line contacts and storage node contacts. U.S. Pat. Nos. 5,670,404 and 5,430,328, et al, the disclosures of which are incorporated herein by reference, disclose SAC techniques for the formation of contact holes.
The continuing trends toward high-density devices require the formation of high aspect ratio contact holes in the cell array region. It is, however, very difficult to form high-aspect ratio contact holes by anisotropically etching oxide layers. To overcome the problems associated with the formation of high aspect ratio contact holes, contact pads are formed for bit line contacts and storage node contacts between the access transistors. Then bit line contacts and storage node contacts are formed in alignment with the underlying contact pads.
Semiconductor memory devices such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), has a memory cell array and a peripheral circuit. In a DRAM device, a memory cell is provided for each bit of information stored by the DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the capacitor. The other drain or source and the transistor gate electrode are connected to external connection lines called bit lines and word lines. The other terminal of the capacitor is connected to a reference voltage.
A peripheral circuit is provided to drive and control the memory cell array. MOS (metal-oxide-semiconductor) transistors in the peripheral circuit are connected to bit lines and local interconnections.
As is well known in the art, in the cell array region, bit line contact holes are formed in the oxide layer down to bit line contact pads. The contact pads are formed between the access transistors in the cell array region by selectively etching the oxide against the nitride comprising sidewall spacers and a capping layer of the access transistor. In the peripheral region, some bit line contact holes are formed in the oxide layer to expose the impurity diffusion region of the MOS transistor, and other bit line contact holes are formed in the oxide layer and the capping nitride layer of the MOS transistor to expose the gate electrode of the MOS transistor. Bit line contact processing in the cell array region uses an etching recipe that etches oxide selectively against the capping and sidewall spacer nitride layers. But, bit line contact holes exposing the gate electrode in the peripheral circuit region requires an etching recipe that etches the oxide and capping nitride layers without etch selectivity therebetween.
Accordingly, if bit line contact holes are formed through a single photolithography process step, some problems can be encountered. For example, misalignment in the cell array region can etch the capping nitride layer of an access transistor in the cell array region when bit line contacts to the gate electrode of the MOS transistor in the peripheral region is formed. This increases shorts between the gate electrode and bit lines in the cell array region. Furthermore, since the cell array region and the peripheral region require different etching conditions, it can be very difficult to control the end point of an etching process. This in turn can undesirably etch the underlying layer exposed by the contact holes.
For this reason, conventionally, bit line contact holes are formed by a two-step photolithographic process. One method is described as follows: The first photolithographic process step forms bit line contact holes in the cell array region to expose the bit line contact pads by selectively etching the oxide layer against the capping nitride layer. The second photolithographic process step forms bit line contact holes in the peripheral circuit region to expose the silicon substrate (i.e., impurity diffusion regions) and the polysilicon (or polycide) of the MOS transistor by the etching the oxide layer and the capping nitride layer, respectively, without an etching selectivity therebetween. An alternative method is described as follows: The first photolithographic process step forms bit line contact holes to expose bit line contact pads in the cell array region and to expose the silicon substrate in the peripheral region by etching the oxide layer selectively against the nitride capping layer and the sidewall spacers formed of nitride. Then the second photolithographic process step forms bit line contact holes to expose the polysilicon (or polycide) of the MOS transistor in the peripheral region. U.S. Pat. Nos. 5,895,239 and 5,918,120 disclose a method for fabricating a DRAM device having a COB (capacitor over bit line) structure.
The above-mentioned methods requiring a two-step photolithographic process is relatively complex and expensive. Also, controlling the end point detection during the etching process can be difficult.
Thus, it is desirable to reduce the required photolithographic process steps to form contact holes.
Therefore, it is an object of the present invention to provide a method of forming bit line contact holes concurrently in the cell array region and the peripheral circuit region through a single-step photolithographic process.
According to the present invention, when bit line contact to a gate electrode of a MOS transistor in the peripheral circuit region is completed (i.e., when the capping nitride layer of the MOS transistor is etched), no further etching is performed (so called xe2x80x9cetching stop phenomenonxe2x80x9d) in the previously-formed bit line contact holes to bit line contact pads in the cell array region and to impurity diffusion region of MOS transistor in the peripheral region. Such an etching stop phenomenon results from the difference in the aspect ratios among contact holes. The aspect ratio of the contact holes to the bit line contact pads in the cell array region and the impurity diffusion region in the peripheral circuit region is greater than that of the bit line contact holes to the MOS transistors in the peripheral circuit region. If the aspect ratio of the contact hole is about 4 or more, substantially no further etching occurs. Accordingly, additional etching to the selected contact holes can be performed to complete the contact holes in the desired layers without unwanted etching of the layer exposed by the contact holes having an aspect ratio of 4 or more.
In accordance with one aspect of the present invention, a method of forming bit line contact holes is provided. The method comprises forming a first transistor in the cell array region and a second transistor in the peripheral region of a semiconductor substrate. Each of the transistors is made of a gate electrode with a capping layer thereon, a source/drain region adjacent the gate electrode and a sidewall spacer on the sidewalls of the transistor. The capping layer and sidewall spacer is formed of nitride. A first insulating layer is formed on the semiconductor substrate including the first and second transistors. The first insulating layer is formed of a material that has an etching selectivity against the capping and sidewall spacer nitride layers.
As an example, an oxide can be used. Conductive pads are formed to electrically connect to the source/drain region of the first transistor through the first insulating layer. The conductive pads are formed by selectively etching the first insulating layer against the nitride layers to form self-aligned contact holes, which exposes the substrate between adjacent first transistors. Then, a conductive material is deposited in the self-aligned contact holes and on the first insulating layer. Next, the conductive material is planarized to form the conductive pads. A second insulating layer is formed over the first insulating layer including the conductive pads and first and second transistors. The second insulating layer is formed of a material, such as an oxide, which has an etching selectivity against the nitride layer. First, second and third contact holes or openings are formed to expose a top surface of the semiconductor substrate (i.e., source/drain region of the second transistor) in the peripheral region, a top surface of the gate electrode of the second transistor in the peripheral region, and a top surface of the conductive pads in the cell array region, respectively.
More particularly, the first and second insulating layers are first-selectively etched against the capping and sidewall spacer nitride layers using a mask pattern, to form the first and third contact holes that respectively expose the top surface of source/drain region of the second transistor and the top surface of the conductive pad in the cell array region. This step also forms a second contact opening that exposes a top surface of the capping layer of the second transistor. It is preferable that an aspect ratio of the first and third contact holes is at least 4 and an aspect ratio of the second contact opening is less than 4. Then, the exposed capping layer of the second transistor in the peripheral region is second-etched using the same mask pattern until the top surface of the gate electrode of the second transistor is exposed, to complete the second contact holes. No further etching occurs in the first and third contact holes due to a high aspect ratio of 4 or more. Accordingly, first, second and third contact holes to the source/drain region of the second transistor, to the gate electrode of the second transistor and to the conductive pad can be concurrently formed using a single-step photolithographic process.
Preferably, the first-selectively etching of the first and second insulating layers against the capping layer and sidewall spacers uses a mixed gas containing C4H8, CO and argon, and the second-etching of the exposed capping layer uses a mixed gas containing a CHF3, CO and argon. Alternatively, the first-selectively etching uses a mixed gas containing C4H8, CO and argon, and the second-etching uses a mixed gas containing a CHF3, CO and O2.